1. Field of the Invention
The present invention generally relates to a semiconductor package and more particularly to a standing chip scale package.
2. Description of Related Art
The miniaturization of electronic devices has led to the design and manufacture of increasingly smaller semiconductor devices. Semiconductor devices are generally packaged for electrical connection to traces of a printed circuit board. Chip scale packages provide a package on the scale of the semiconductor device to minimize board space consumed by the package.
Vertical conduction power semiconductor devices such as MOSFETs generally have two electrodes or contacts formed on a first surface of the device and a third electrode or contact formed on a second surface of the device. In order to electrically connect the electrodes to the printed circuit board, some conventional chip scale packages provide a means by which all the electrodes are disposed on the same side of the device. For example, U.S. Pat. No. 6,646,329 discloses a package including a leadframe and a die coupled thereto. The die is coupled to the leadframe such that its back surface (drain contact) is coplanar with source leads and a gate lead extending from the leadframe. The disclosed structure is disadvantageously complex.
Another prior art chip scale package includes a die mounted drain side down in a metal clip or can with the source and gate electrodes disposed coplanar with the rim surface of an extended portion of the clip or can as disclosed in U.S. Pat. No. 6,767,820. The disclosed package makes it difficult to visually check solder joints after the package is mounted onto a circuit board.
A flip-chip MOSFET structure disclosed in U.S. Pat. No. 6,653,740 has a vertical conduction semiconductor die in which the lower (drain) layer of the die is connected to a drain electrode on the top of the die by a diffusion sinker or conductive electrode. The disclosed structure suffers the problem of increased resistance and a reduced active area.
It is also known to electrically connect the device electrodes with the printed circuit board by means of conductive blocks or layers. One such structure is disclosed in U.S. Pat. No. 6,392,305 wherein the electrodes of the chip are electrically connected to conductive blocks that in turn are connected to the printed circuit board through side surfaces thereof. U.S. Pat. No. 6,841,416 discloses a chip scale package having upper and lower conductive layers connected to the terminals of the chip. Electrode surfaces formed on the same side surfaces of the upper and lower conductive layers are connected to corresponding connection pads of the printed circuit board. The disclosed structures are overly complex and/or the fabrication process is too complicated and/of inefficient for low cost production.
There remains a need in the art for a chip scale package that provides electrical connection to device contacts on both sides of the chip, a clear view of solder joints, and a reduced printed circuit board mounting area. Preferably the process of fabricating the chip scale package permits batch handling. Further, the chip scale package can preferably be made using simple manufacturing steps and at low cost.